Today, the Plasma technology makes it possible to achieve flat colour panels of large size and with very limited depth without any viewing angle constraints. The size of the displays may be much larger than the classical CRT picture tubes.
Referring to the last generation of European TV, a lot of work has been done to improve its picture quality. Consequently, a new technology like the Plasma one has to provide a picture quality as good as or better than the old standard TV technology. In the field of picture quality, the brightness of the screen is of paramount importance.
However, the electronic parts of the actual plasma technology give rise to electromagnetic radiation. In order to assure the compatibility of PDP (plasma display device) products with other electronic components (VCR, DVD, PC, Mobile phone . . . ), it is necessary to put a filter in front of the screen. Two major sources of radiation exist:                Sustain frequency (a solution is not subject of the current document)        Data driving (a solution is presented in the current document)        
For the rest of the document, the case of a standard PDP using 40 MHz data drivers shall be considered in order to simplify the exposition. The selling of such a product requires given norms to be respected in the fields of radiation as shown FIG. 1, for the case of data drivers working at 40 MHz and high content screen (cell R, G, B alternately ON and OFF).
The limit for consumer applications according to the European norm is depicted in the figure (class B norm). One peak linked to the data driver frequency (40 MHz), exceeds the limit of the norm. In order to fulfil the requirements of the norm, a front filter may be applied in front of the panel. One goal of this filter is to suppress the EMI (Electro-Magnetic Interference) using the so-called faraday principle: the filter is a transparent layer covered by a thin grid of metal. The basic assembly of a screen with a filter is illustrated in FIG. 2. The panel 1 together with the drivers 2 and the power electronic 3 is arranged in a housing 4 which stops the EMI at the backside of the display device. The front filter 5 in front of the panel 1 stops the EMI emitted from the front side of the panel.
Nevertheless, this filter 5 has only a reduced transparency with an actual value between 50% and 60% for consumer applications (for professional applications the norm is not so strict and the transparency is better: 65% to 75%). This filtering is really mandatory since if the front filter is removed from a plasma panel, even an IR remote control is not able to work properly. In other words, if the brightness shall be increased as well as the addressing speed also the radiation will be increased, that will require a stronger filter with even less transparency.
For further reducing the EMI related to the data driving it is necessary to know some aspects of PDP data driving.
In order to activate the plasma cells before lighting a first stage called writing or addressing stage has to be performed. During this stage, each line electrode (compare FIG. 3) of the PDP will be selected one after the other by respective drivers Line Driver 1, Line Driver 2 etc. During each selection, binary data information (cell ON or OFF) will be given on all the data electrodes Y (column electrodes) at one time. To do that, the column electrodes Y are linked to so-called data drivers Data Driver 1 to Data Driver 27 which act as registers (serial input and parallel output) working at a given data clock (e.g. 40 MHz in the present example). The line and data drivers are controlled and driven by PDP controller. Furthermore, the line electrodes X are arranged on a front plate of a PDP and the column electrodes Y on the back plate. In the concrete case of a single scan WVGA PDP having a screen with 852 pixels×480 lines 852×3 (R+G+B)=2556 cells have to be written through data drivers. Today drivers have commonly two parallel inputs and 96 parallel outputs to the column electrodes Y so that 48 clocks are needed to load the driver (48/40=1.2 μs). Finally, since 2556/96=26.625, 27 data drivers are required to write all the cells. The 36 data outputs that are in excess, will not be connected but will be filled up with zeros (OFF) from the plasma control IC.
In this connection it has already been proposed to have a jitter in the data clock. This means that various clocks for each cell at each point of time are used. In that case a jitter generator is added on the data driver clock with a kind of random effect. However, one has to guarantee that the overall loading speed will not exceed the expected writing speed. Such appliance of jitter is not very efficient.
Moreover, according to the document EP 1 365 382 various addressing time periods per line may be used as shown in FIG. 4. The length of the addressing period is different from line to line. Concerning the evolution of the addressing time per line there are three categories of dependency:                A panel homogeneity dependency: this parameter is related to the fact that the panel does not have the same behaviour among the whole screen.        A dependency of priming efficiency: the priming operation enables a rapid writing but its efficiency could decrease in time (depending on panel technology).        A dependency of sustain efficiency: the writing operation is directly followed by the sustain operation. Since the efficiency of the writing operation is linked to the capacity effect of the panel, this could change with the delay to the sustain operation.        
In the amount of sub-fields there may be two different categories as already explained in a previous document EP 1 250 696:                Sub-field preceded by a priming also called primed sub-field (PSF)        Sub-field not preceded by a priming also called refreshing sub-field (RSF)        
In FIGS. 5 and 6 two examples of addressing time per PDP lines for the two previous categories of sub-fields are depicted.
FIG. 5 shows an example of the overall addressing speed for a primed sub-field. In a region around line 160 the addressing time is lower than 1 μs per line. At the large line numbers the addressing time per line increases rapidly.
In contrast to that FIG. 6 shows an example of the overall addressing speed for a non-primed sub-field. Although the addressing time is always larger than 1 μs per line it does not essentially increase at the large line numbers.
Obviously, depending on the panel technology, the curve of the addressing speed can have different behaviours. All the curves presented here are only examples related to a specific technology. In any case, a characterization of the panel speed should be made specifically for each technology and each new process.
However, according to the technology introduced in EP 1 365 382 only the addressing speed was changed. In other words, the clock of the data drivers should correspond to the fastest addressing period per line to suit various addressing speeds as disclosed in EP 1 365 382:                In case of FIG. 5, the fastest addressing speed is 0.93 μs requiring a data driver working at 51.61 MHz.        In case of FIG. 6, the fastest addressing speed is 1.23 μs requiring a data driver working at 39.02 MHz.        
Indeed, it is necessary to have the data drivers (compare FIG. 3) loaded before writing (i.e. addressing) the line and so the only requirement is to have a loading speed smaller than the addressing period. The loading speed and consequently the data driver clock is kept constant. However, this has a dramatic impact on the EMI as explained in the introduction.